Tomo Pop Blog

Architect Glasgow in the first gate arrays, the easiest and un-specific way of providing this capability is to employ a transistor as the basic logic part, and build gates and storage elements from it.

This approach was indeed tried in a commercial FPGA from the now-defunct company Crosspoint [144]. This kind of very fine-grained logic block , however ,needs the use of large amounts of programmable interconnect to make any typical logic function.

It will end up in an FPGA that is certain to suffer from area-inefficiency ( because programmable routing is pricey in terms of area ), low performance ( each routing’hop’ is slow ), and high energy consumption ( thanks to the higher capacitance of programmable interconnect that has got to be charged and discharged ).

At the other acute, a logic block may be a complete processor. This approach exists in the commercial space, although processors are mixed with some more fine grained logic blocks in a device [13, 188, 189, 195, 196, 228, 231, 235].

Such a logic block on its own wouldn’t have the performance gains that come from customizable hardware.

FPGA designers over the last twenty years have chosen basic logic blocks made of transistors ( noted above ) [144], NAND gates [160], an interconnection of multiplexers [79], lookup tables [49], and PAL-style wide-input gates [217]. These choices were originally driven by intuitive revelations on the part of architects, often with little info or analysis, with a few exceptions [79].

In this debate, we use silicon area as the proxy for cost, as is common. These structures are very efficient at implementing express.

quote Architect Glasgow Lvj